SPIE=0, SPE=0, SPTIE=0, MSTR=0, CPOL=0, CPHA=0, LSBFE=0, SSOE=0
SPI Control Register 1
| LSBFE | LSB First (shifter direction) 0 (0): SPI serial data transfers start with the most significant bit. 1 (1): SPI serial data transfers start with the least significant bit. |
| SSOE | Slave Select Output Enable 0 (0): When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input. 1 (1): When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input. |
| CPHA | Clock Phase 0 (0): First edge on SPSCK occurs at the middle of the first cycle of a data transfer. 1 (1): First edge on SPSCK occurs at the start of the first cycle of a data transfer. |
| CPOL | Clock Polarity 0 (0): Active-high SPI clock (idles low) 1 (1): Active-low SPI clock (idles high) |
| MSTR | Master/Slave Mode Select 0 (0): SPI module configured as a slave SPI device 1 (1): SPI module configured as a master SPI device |
| SPTIE | SPI Transmit Interrupt Enable 0 (0): Interrupts from SPTEF inhibited (use polling) 1 (1): When SPTEF is 1, hardware interrupt requested |
| SPE | SPI System Enable 0 (0): SPI system inactive 1 (1): SPI system enabled |
| SPIE | SPI Interrupt Enable: for SPRF and MODF (when FIFO is not supported or not enabled) or for read FIFO (when FIFO is supported and enabled) 0 (0): Interrupts from SPRF and MODF are inhibited-use polling (when FIFOMODE is not present or is 0) or Read FIFO Full Interrupts are disabled (when FIFOMODE is 1) 1 (1): Request a hardware interrupt when SPRF or MODF is 1 (when FIFOMODE is not present or is 0) or Read FIFO Full Interrupts are enabled (when FIFOMODE is 1) |